1. Field of the Invention
The invention relates to a monocrystalline semiconductor wafer having regions with a very low and homogeneous density of GOI-relevant defects. The invention also relates to a method for annealing GOI-relevant defects in a monocrystalline semiconductor wafer, wherein at least one side of the semiconductor wafer is irradiated by means of a laser.
2. Background Art
Semiconductor wafers, in particular silicon wafers, are generally used for producing microelectronic components. In the semiconductor industry, and in particular in silicon technology, which has advanced very far scientifically and also technologically, the quality requirements of the semiconductor wafers increase further and further as time goes on, in view of the ever further decreasing smallest feature sizes of the microelectronic components.
In order to meet these requirements, several types of very low-defect semiconductor wafers were developed: polished semiconductor wafers produced from extremely low-defect single crystals (e.g. EP0972094B1), thermally treated semiconductor wafers (e.g. EP0829559B1) or semiconductor wafers having an epitaxially deposited silicon layer.
It has been found, however, that even the best semiconductor wafers known at the present time pose problems in specific applications, such as, for example, SOI (Silicon On Insulator), Strained Silicon or sSOI (strained Silicon On Insulator), associated with line widths (design rule) <100 nm during production or during operation of the components. Thus, leakage currents, short circuits, deviating diode characteristic curves, hot spots, gate oxide failure or poor reliability of the components lead to failure. This is described comprehensively and extensively in the literature, for example:
It is thus described that ingrown vacancy clusters lead to problems in the reliability of the gate oxide [K. Yamabe, K. Taniguchi, Y. Matsushita, in PROC. OF THE INTERNAT. RELIABILITY PHYS. SYMP., IEEE, NJ, 184 (1983)], component isolation faults [M. Muranaka, K. Makabe, M. Miura, H. Kato, S. Ide, H. Iwai, M. Kawamura, Y. Tadaki, M. Ishihara, T. Kaeriyama, JPN. J. APPL. PHYS., 37, 1240 (1998)] and faults in memory trenches [E. Dornberger, D. Temmler, W. v. Ammon, J. ELECTROCHEMICAL SOCIETY 149, G226-G231 (2002)]. These problems are aggravated with increasing structure miniaturization—particularly when the vacancy clusters reach the magnitude of typical component magnitudes such as e.g. gate lengths. Vacancy clusters lead to tiny pits in SOI structures and to holes in very thin silicon films, and are thus “killer defects” [G. K. Keller, S. Cristoloveanu, J. APPL. PHYS. 93, 4955 (2003)].
The semiconductor wafers mentioned above can only inadequately meet the demands imposed by future generations of components, in particular as far as the areal and local properties of the defect homogeneity are concerned.